Formal Equivalence Checking and Design Debugging

€229.00
+ €5.99 Shipping
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Formal Equivalence Checking and Design Debugging

Formal Equivalence Checking and Design Debugging

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Formal Equivalence Checking and Design Debugging

  • Brand: Unbranded

€229.00

In stock
+ €5.99 Shipping

14-Day Returns Policy

Sold by:

€229.00

In stock
+ €5.99 Shipping

14-Day Returns Policy

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Description

Formal Equivalence Checking and Design Debugging

1 Introduction. - 1. 1 Problems of Interest. - 1. 2 Organization. - I Equivalence Checking. - 2 Symbolic Verification. - 3 Incremental Verification for Combinational Circuits. - 4 Incremental Verification for Sequential Circuits. - 5 AQUILA: A Local BDD-based Equivalence Verifier. - 6 Algorithm for Verifying Retimed Circuits. - 7 RTL-to-Gate Verification 123. - II Logic Debugging. - 8 Introduction to Logic Debugging. - 9 ErrorTracer: Error Diagnosis by Fault Simulation. - 10 Extension to Sequential Error Diagnosis. - 11 Incremental Logic Rectification. Language: English
  • Brand: Unbranded
  • Category: Education
  • Artist: Shi-Yu Huang
  • Format: Paperback
  • Language: English
  • Publication Date: 2012/09/30
  • Publisher / Label: Springer
  • Number of Pages: 229
  • Fruugo ID: 343652760-752833792
  • ISBN: 9781461376064

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  • STANDARD: €5.99 - Delivery between Mon 26 January 2026–Thu 29 January 2026

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